Fred Weber AMD VP and CTO, Computation Products Group

Towards Instruction Set Consolidation
San Jose, CA
October 15, 2003
8:35 AM PDT


This keynote will examine the evolution of microprocessor instruction set architectures. Where have we been, where are we now, and most importantly, where are we going? What trends might evolve within microprocessor instruction architecture? What are the economic impacts of those trends, and what are the implications for the industry?



Keynote Supporting Materials
View the Presentation Slides


View the Presentation Video:

Executives from Tiqit Computers speak on extending the x86 instruction set architecture.

Long version (7:34 min, 5MB)
Short version (3.13 min, 2MB)

About Fred Weber
Fred Weber is Vice President and Chief Technical Officer of AMD's Computation Products Group. Weber came to AMD in 1995 with the acquisition of NexGen and was instrumental in bringing AMD’s high performance AMD-K6® and AMD Athlon™ microprocessors to market. His foresight into the challenges involved in creating microprocessors with millions of transistors and his expertise in microprocessor design led to the development of a design methodology that has helped AMD create the AMD Opteronä and the AMD Athlonä 64 processors. He studied physics and systems engineering at Harvard University and received a Bachelor’s degree in physics.


About Microprocessor Forum 
For nearly 20 years, Microprocessor Forum has been a premier conference and technology expo geared towards technical and engineering professionals. The event provides insights for designers and engineers to understand the significance of new processor architectures and their effect on the microprocessor industry. Microprocessor Forum is presented by In-Stat/MDR.